Who is eligible to attend?
All interested CE, EE, and related fields students are welcome to attend. The contest will be held in separate undergraduate and graduate levels. No pre-requisite is mandated.

Which designs are approvable?
The contest is open to any new idea provided that it is based on FPGAs. Use of any FPGA and FPGA development board is allowed; however, CE department provides you with Altera UP1 development boards (based on MAX7128 and FLEX10K50 chips) and required EDA tools and facilities for free.
A list of sample designs and their definitions is available.


Mar. 5th:
The prize is raised to 8 Full Gold Coins for 4 teams.
Mar. 5th: Deadline for the final presentation is extended to March 13th.
Jan. 29th: Judgment criteria are defined.
Jan. 29th: The contest prize is increased.
Jan. 12th: Proposals are judged.
Jan. 8th: Proposals are under review.
Jan. 2nd: No Deadline for proposal submission

What are the contest steps?
This is an off-line contest. The participating teams are given an almost 2-month period to physically implement their designs. Then, each team presents a technical paper describing his detailed design and achieved results. At the judgment day, all teams present their design in front of the audience and the scientific committee, and the winner is introduced and prized at the end.
All required equipments, facilities, and tools will be provided by the CE department for all registered teams.

How can I attend?
Choose one of our proposed designs or submit a proposal for your desired design before the deadline. Your proposals will be judged for technical and financial feasibility and you’ll be informed of the result. After proposal approval, you can register online for free, and start implementing your design while respecting the contest participation rules.